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Trusted Irix /B 4.0.4
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Trusted-Irix B-4.0.1.iso
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eoe1.idb
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usr
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include
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sys
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gr2.h.z
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gr2.h
Wrap
C/C++ Source or Header
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1992-04-03
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8KB
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291 lines
#ifndef __SYS_GR2_DEV_H__
#define __SYS_GR2_DEV_H__
/*
* $Revision: 1.50 $
*/
#include "gfx.h"
#include "rrm.h"
#ifdef IP17
#define GFX_NAME_GR2 "GR2MP" /* Unique name for GR2 type boards */
#else
#define GFX_NAME_GR2 "GR2" /* Unique name for GR2 type boards */
#endif
struct gr2_info {
struct gfx_info gfx_info; /* device independent information */
unsigned char BoardType; /* 0 for a GR2, 1 for HI1 */
unsigned char Bitplanes; /* 8 or 24 */
unsigned char Auxplanes; /* 2 or 4 */
unsigned char Wids; /* 2 or 4 */
unsigned char Zbuffer; /* true if zbuffer option installed */
unsigned char MonitorType; /* monitor id & setmon state */
unsigned char GfxBoardRev;
unsigned char PICRev;
unsigned char HQ2Rev;
unsigned char GE7Rev;
unsigned char RE3Rev;
unsigned char VC1Rev;
unsigned char VidBckEndRev;
unsigned char Xabnormalexit; /* X killed without closing file
descriptor. */
unsigned char GEs; /* 1 or 4 */
};
/*
* XXX If change Gr2PixelDma() or any of these defines, check the others!
*/
#define DMAMAXXLEN 1280 /* Max x length for pixel DMA */
#define DMAMAXYLEN 1024 /* Max y length for pixel DMA */
#define GR2_GFXPG_VADDR 0x1000 /* Used in gl - virtual graphics address */
#ifdef _KERNEL
#define GR2_BASE_PHYS 0x1F000000 /* private bus GR2 board family base
* physical addr */
#define GR2_3WAY_SIZE 0x2000
#define GR2_GFX_SIZE 0x6D000
#define GR2_MAP_SIZE (GR2_GFX_SIZE + GR2_3WAY_SIZE)
/* size of region to map into graphics
* process's address space */
/* GR2 variants; -1 means probe failed */
#define GR2_TYPE_NOT_THERE -1 /* probe failed */
#define GR2_TYPE_GR2 0 /* Express GR2 */
#define GR2_TYPE_HI1 1
/*
* Change the timing table as screen x coord of cursor crosses this x value.
* This value must be < 1024, since for high res. 1024+250bp = 1280,
* which is the max range of CUR_XL.
* Be aware when changing this value which side of the "border" the cursor
* will be on when the xserver starts up. Set the GR2_VID_EP for the correct
* timing table in the VC1 initialization, accordingly.
*/
#define GR2_CURS_CHNGE_TIMING 32
/*
* XXX If change Gr2PixelDma() or any of these defines, check the others!
*/
#define PGSPERSHOT 32 /* Number pages map/lock at a shot*/
#define MAXPERSHOT (NBPC * PGSPERSHOT) /* Max bytes map/lock at a shot */
#define CXDMAPAGES 20
struct gr2_data {
struct gfx_data gfx_data; /* Common gfx driver above */
struct gr2_info *info; /* gr2 inventory */
struct gr2_hw *base; /* K1 seg board base address */
unsigned int attaches;
int cursor_x; /* x passed by Xserver*/
int cursor_y; /* y passed by Xserver*/
int cursor_xhot; /* x hot position */
int cursor_yhot; /* y hot position */
int mon_xoffset; /* mon. dependent horizontal offset*/
int mon_yoffset; /* mon. dependent vertical offset*/
void *Retrace ;
sema_t dmalock;
void *dmadap; /* DMA descriptor array for pixels */
void *cxdmadap; /* DMA descriptor array for context
switching */
/* The owner of the data buffer */
struct rrm_rnode *scratchrn;
struct rrm_rnode *nurbsrn;
struct rrm_rnode *spotlightrn;
struct rrm_rnode *volumern;
unsigned long loadedmodes[32];
#ifdef IP17
unsigned void *adapter_base; /* kernel address of base address of adapter board */
int adapter_slot; /* MP slot id of adapter (only on MP bus systems)*/
int gio_slot; /* MP slot id of GIO (only on MP bus systems)*/
#endif
};
/*
* device dependent rendering node
*/
struct gr2_rnode {
/* Context switch stuffs */
long user_finish;
long pcxtype; /* New, GE, Host, Dump */
unsigned long pcxsize; /* Small, Light */
unsigned long newpcxsize;
struct RRM_ValidateClip validateclip;
long pcxdatatype; /*
bit 0 - DATA_NURBS
bit 1 - DATA_SPOTLIGHT
bit 2 - DATA_VOLUME
bit 3 - DATA_TEXTURE
bit 4 - DATA_VOLUME8K
bit 5 - DATA_VOLUME16K
bit 6 - DATA_SCRATCH
*/
/* all kinds of data buffer */
void *scratchp;
unsigned long scratch_datasize;
unsigned long scratch_bufsize;
void *nurbsp;
unsigned long nurbs_size;
void *spotlightp;
unsigned long spotlight_size;
void *volumep;
unsigned long volume_size;
/* XXX add VOLUME8K, VOLUME16K later */
/* Retrace stuffs */
unsigned long swapinterval; /* Min. retraces between swapbuffers */
unsigned long nextswap; /* Retrace count value to swapbuffers at */
struct gr2_cyclemap *cyclemap; /* malloced array of 16 when used */
unsigned long cyclemap_curmap;
unsigned long cyclemap_nexttime;
struct gr2_blink *blink; /* malloced array of 20 when used */
struct rrm_rnode *nextintervalrnp;
#ifdef IP17
/* MG1 board control registers */
unsigned long mg1_control1;
unsigned long mg1_control2;
/* IP17 3way registers */
unsigned long ip17p3way_cntcmdreg; /* only 16 bits are valid */
unsigned long ip17p3way_ABCDregs[4];
#endif
};
#endif /* _KERNEL */
/*
* GR2 specific (gf_Private) Ioctls
*/
#define GR2_BASE 15000
#define GR2_SETCURSOR_HOTSPOT (GR2_BASE+3)
#define GR2_SETMONITOR (GR2_BASE+5)
#define GR2_SETGAMMARAMP (GR2_BASE+6)
#define GR2_GETMONITOR (GR2_BASE+8)
#define GR2_PIXELDMA (GR2_BASE+10)
#define GR2_CHANGECXSIZE (GR2_BASE+11)
#define GR2_TEXTUREDMA (GR2_BASE+12)
#define GR2_ACCUMULATE (GR2_BASE+13)
#define GR2_ACRETURN (GR2_BASE+14)
#define GR2_ALLOCCXDATA (GR2_BASE+15)
#define GR2_SETDISPLAYMODE (GR2_BASE+16)
/*
* GR2 Ioctl args
*/
struct gr2_colorentry {
unsigned short index;
unsigned char red;
unsigned char green;
unsigned char blue;
unsigned char junk; /*XXX What is this?*/
};
struct gr2_setcolor_args {
short numberofcells;
struct gr2_colorentry colors[1];
};
struct gr2_setdisplaymode_args {
long int wid;
unsigned long int displaymode;
};
struct gr2_blankscreen_args {
int blank; /* 0 on, 1 off, 2 query */
};
/* Flags for graphics DMA */
#define GR2_WRITE 0x01 /* DMA direction: host to gfx */
#define GR2_STRIDE 0x02 /* Stride DMA */
#define GR2_TTOB 0x04 /* Pixels dma'ed from top to bottom */
#define GR2_RTOL 0x08 /* Pixels dma'ed from right to left */
#define GR2_ZOOM 0x10 /* Zoomed pixels */
#define MAXDMADA 200 /* The maximum DMA descriptor arrays
for simulation */
struct gr2_pixeldma_args {
long token; /* Token to send down pipe */
long x; /* Rectangular coordinate in pixels */
long xlen;
long y;
long ylen;
unsigned short flags; /* Bit flags defined below */
long pmstride; /* Number of 32-bit CPU words per
scanline */
long yzoom; /* Zoom factor in Y */
long nbytes; /* Total bytes of DMA,
stride = pmstride * ylen * 4;
non-stride = wlen * ylen * 4
*/
long wlen; /* # of dma words (in words) */
char *buf; /* Data buffer */
};
struct gr2_setcursor_hotspot_args{
unsigned short xhot; /* X cursor hotspot */
unsigned short yhot; /* Y cursor hotspot */
};
struct gr2_acbufdma_args {
long token; /* GL token */
long x; /* accumulation buffer area */
long xlen;
long y;
long ylen;
long scale;
long *buf;
};
struct gr2_alloccxdata_args {
long datatype;
};
struct gr2_getcmap_args {
unsigned int start;
unsigned int size;
unsigned char *buffer;
};
struct gr2_getoverlaycmap_args {
unsigned int size;
unsigned char *buffer;
};
struct gr2_setgammaramp_args {
unsigned char red[256];
unsigned char green[256];
unsigned char blue[256];
};
/* Monitor types - for setmonitor */
/* IMPT: Xserver assumes that interlaced monitors have the low bit set to 1.*/
#define GR2_HZ60 0
#define GR2_NTSC 1 /* Interlaced */
#define GR2_STR_RECT 2
#define GR2_PAL 3 /* Interlaced */
#define GR2_HZ72 4
/* Flags for genlock */
#define GR2_GENLOCK_IN 0x01
struct gr2_monitor_args {
unsigned long monitortype;
unsigned char flag;
};
#endif /* __SYS_GR2_DEV_H__ */